This paper addresses the simulation of fundamental logic gates (e.g. AND, OR, NOT) using the software PowerRPDEVS that is based on the Revised Parallel Discrete Event System Speci1cation (RPDEVS) formalism. The formal differences of the models of a NOR gate in RPDEVS and PDEVS are analyzed. It is further shown, which possible pitfalls may occur when connecting these logic gates with feedbacks that cause algebraic loops and in which cases these algebraic loops are resolved by the RPDEVS simulation algorithm. For this purpose, a static RS flop-flop, a triggered D flip-flop and a shift register are modeled and simulated in PowerRPDEVS. The results are compared to previous research about the simulation of such logic circuits in Simulink and Modelica.